Search results for "Fault coverage"
showing 5 items of 5 documents
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques
2004
Modern processors tend to increase the number of registers, being part of them not accessible by the instruction set. Traditionally, the effect of faults in these hidden registers has not been considered during system validation using fault injection. In this paper, a study of the importance of faults in hidden registers is performed. Firstly, we have analysed the sensitivity of hidden registers to faults in combinational logic. In a second phase, we have analysed the impact of the faults occurred in hidden registers on system behaviour. A broad set of permanent and transient faults have been injected into the models of two typical commercial microcontrollers, using a VHDL-based fault injec…
Towards online bearing fault detection using envelope analysis of vibration signal and decision tree classification algorithm
2017
Online bearing fault detection is an important method for monitoring the health status of bearings in critical machines. This work proposes a classification algorithm, which can be extended towards an online bearing fault detection. The objective is to detect and classify the bearing faults in early stages. The overall design aspects of the online bearing fault detection and classification system are discussed. The proposed method is validated using experimental data, and a high accuracy of the fault classification was observed. Therefore, the proposed method can be applied for an online early fault detection and classification system.
Using partial-orders for detecting faults in concurrent systems
1998
The paper suggests test derivation approaches to obtain test suites for concurrent systems based on the concept of fault coverage criteria in opposition to structural test coverage criteria. Using a partial-order model, called Mazurkiewicz Trace Machine (MTM), for test derivation, the state explosion problem can be alleviated. The derived test suites are characterized by their small size compared to test suites from traditional test derivation approaches and exhibit a defined degree of fault coverage according to certain fault models. The fault models of concurrent systems considered in the paper are based on the most common faults, acceptance, refusal, and transfer faults. A scenario of te…
A Geometrical Simple Approach for Power Silicon Devices Fault Detection and Fault-Tolerant Operation of a Voltage Source Inverter
2012
Fault-tolerant converters have been widely investigated for years and nowadays an extensive technical literature on this field exists. This paper presents a novel fault detection algorithm based on a simple geometrical approach. In the algorithm analysis both the case of faults in single device and the lose of an entire inverter leg have been considered. False positive detections are avoided by considering a proper number of current samples. The proposed fault detection algorithm is characterized by simplicity, low computational and implementation effort with a consequent enough fast execution, easy control integration with the possibility to use it both in hardware in the loop systems and …
Fault Injection into VHDL Models: Experimental Validation of a Fault-Tolerant Microcomputer System
1999
This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed with this purpose. We have carried out a set of injection experiments (with 3000 injections each), injecting transient and permanent faults of types stuck-at, open-line and indetermination on both the signals and variables of the system, running a workload. We have analysed the pathology of the propagated errors, measured their latency, and calculated both detection and recovery coverage. We have…